Methods of Fabricating Nonvolatile Memory Devices

ABSTRACT

Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.11/403,964, filed Apr. 13, 2006, which claims priority to Korean PatentApplication No. 10-2005-0031153, filed on Apr. 14, 2005 in the KoreanIntellectual Property Office, the disclosures of which are herebyincorporated herein by reference as if set forth in their entirety.

FIELD

The present invention relates to semiconductor devices and methods offabricating the same, and more particularly, to nonvolatile memorydevices and methods of fabricating the same.

BACKGROUND

Generally, nonvolatile memory devices are configured to store and erasedata electrically and retain the stored data even if a power supply tothe memory device is interrupted. Nonvolatile memory devices typicallyhave a stacked gate electrodes including a gate insulating layer, afloating gate, a dielectric layer and a control gate sequentiallystacked gate structure on an active region of a substrate. In order toeasily program and/or erase data from the memory device a coupling ratioshould typically be high. The coupling ratio may be represented as aratio between a voltage applied to the control gate and a voltageinduced to the floating gate. Typically, the coupling ratio may beincreased by having the dielectric layer and the control gate beadjacent to a side surface as well as a upper surface of the floatinggate.

Referring to FIGS. 1A to 1C, cross-sections of memory devicesillustrating conventional methods of increasing the coupling ratio willbe discussed. As illustrated in FIG. 1A, an active region is defined ona substrate 10 by an isolation layer 16. A gate insulating layer 12 anda floating gate pattern 14 are formed on the active region. The sidesurface of the floating gate pattern 14 is exposed by etching theisolation layer 16 in order to possibly increase the coupling ratio. Atthis time, the etching of the isolation layer 16 may be performed using,for example, a dry etching process, a wet etching process, or the like.When a wet etching process having isotropic etching characteristic isused, the gate insulating layer 12 may be also etched during the wetetching process used to expose the side surface of the floating gatepattern 14.

Therefore, the isolation layer 16 is etched using a two step process.Referring first to FIG. 1B, a first etching process may be performedusing, for example, a dry or wet etching process, on the isolation layer16 a until at least a portion of the gate insulating layer 12 isexposed. As illustrated in FIG. 1C, a second etching process isperformed using a dry etching process having anisotropic etchingcharacteristic in order to etch the isolation layer 16 b around the gateinsulating layer 12. In this case, however, charges generated due toplasma, which may be used as an etchant during the dry etching process,may be accumulated in the floating gate pattern 14. Furthermore, becauseof a strong electric field due to the accumulated charges, a breakdownmay be induced in the thin gate insulating layer 12. This breakdown inthe gate insulating layer 12 may be detrimental to the characteristicsof a transistor, which may cause instability in the operation of thenonvolatile memory device.

SUMMARY

Some embodiments of the present invention provide methods of fabricatingnonvolatile memory devices. An isolation layer is formed on a substrate.The substrate has a memory region and a well contact region and theisolation layer defines an active region of the substrate. A gateinsulating layer is formed on the active region. The gate insulatinglayer is patterned to define an opening therein. The opening exposes atleast a portion of the well contact region of the substrate and acts asa charge pathway for charges generated during a subsequent etch of theisolation layer.

In further embodiments of the present invention, a first conductivelayer may be formed on the gate insulating layer. The isolation layermay be selectively etched to expose at least a portion of a side surfaceof the first conductive layer.

In still further embodiments of the present invention, a dielectriclayer may be formed on the first conductive layer. A second conductivelayer may be formed on the dielectric layer. The dielectric layer andthe first and second conductive layers may be patterned to providestacked gate electrodes on the memory region and the well contact regionof the substrate. In some embodiments, the opening is under the stackedgate electrode formed on the well contact region and electricallycouples the first conductive layer and the substrate. In furtherembodiments, the opening is outside of the stacked gate electrode formedon the well contact region.

In some embodiments of the present invention, a buffer conductive layermay be formed on the gate insulating layer. The buffer conductive layermay be patterned to define the opening in the gate insulating layer andthe buffer conductive pattern.

In further embodiments of the present invention, the isolation layer maybe etched until a surface of the isolation layer is substantially planarwith an upper surface of the first conductive layer. Then, the isolationlayer may be etched until the side surface of the first conductive layeris exposed. The etching of the isolation layer until the side surface ofthe first conductive layer is exposed may include an anisotropic dryetching process.

Although embodiments of the present invention are discussed aboveprimarily with respect to method embodiments, related devices are alsodiscussed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are cross-sections illustrating conventional methods ofincreasing a coupling ratio.

FIG. 2 is a plan view of nonvolatile memory devices according to someembodiments of the present invention.

FIGS. 3A to 11A are cross-sections taken along the line A-A′ of FIG. 2illustrating processing steps in the fabrication of nonvolatile memorydevices according to some embodiments of the present invention.

FIGS. 3B to 11B are cross-sections taken along the line B-B′ of FIG. 2illustrating processing steps in the fabrication of nonvolatile memoirdevices according to the some embodiments of the present invention.

FIG. 12 is a plan view of nonvolatile memory devices according tofurther embodiments of the present invention.

FIGS. 13A to 16A are cross-sections taken along the line A-A′ of FIG. 12illustrating processing steps in the fabrication of nonvolatile memorydevices according to further embodiments of the present invention.

FIGS. 13B to 16B are cross-sections taken along the line B-B′ of FIG. 12illustrating processing steps in the fabrication of nonvolatile memorydevices according to further embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT INVENTION

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. In the drawings, the size and relativesizes of layers and regions may be exaggerated for clarity. It will beunderstood that when an element or layer is referred to as being “on”,“connected to” or “coupled to” another element or layer, it can bedirectly on, connected or coupled to the other element or layer orintervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Like numbers refer to like elements throughout.

It will be understood that although the terms first and second are usedherein to describe various regions, layers and/or sections, theseregions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one region, layer or sectionfrom another region, layer or section. Thus, a first region, layer orsection discussed below could be termed a second region, layer orsection, and similarly, a second region, layer or section may be termeda first region, layer or section without departing from the teachings ofthe present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in the Figures is turned over, elements describedas being on the “lower” side of other elements would then be oriented on“upper” sides of the other elements. The exemplary term “lower”, cantherefore, encompasses both an orientation of “lower” and “upper,”depending of the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The exemplary terms “below” or “beneath” can, therefore,encompass both an orientation of above and below.

Embodiments of the present invention are described herein with referenceto cross-section illustrations that are schematic illustrations ofidealized embodiments of the present invention. As such, variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the preciseshape of a region of a device and are not intended to limit the scope ofthe present invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Referring first to FIG. 2, a plan view of nonvolatile memory devicesaccording to some embodiments of the present invention will bediscussed. As illustrated in FIG. 2, a substrate includes a well contactregion and a memory region. As used herein, the memory region refers tothe portion of the substrate that will be used for a memory cell. Thememory region is formed by, for example, arranging a ground select line54, a plurality of word lines 56 a and 56 b, and a string select line 58on the substrate. The ground select line 54, the plurality of the wordlines 56 a and 56 b, and the string select line 58 cross a plurality ofactive regions defined by isolation layers 106 b. The isolation layers106 b are aligned on the substrate in parallel with one another. Asource region of the ground select line 54 is electrically coupled to acommon source line 52.

The well contact region includes a well contact 60 and a dummy gate line50. The well contact 60 is configured to apply a well bias voltage tothe substrate. A plurality of well contacts 60 may be formed in order todecrease resistance. The well contact 60 may include a gate patternadditionally formed on the well contact region in order to reduce thelikelihood of interference with the lines 52, 54, 56 a, 56 b and 58arranged on the memory region during a patterning process as the spacesbetween the lines 52, 54, 56 a, 56 b and 58 are typically not equal tothe spaces where the well contact 60 is formed. Although in someembodiments of the present invention, the dummy gate lines 50 may beconfigured as the same structure as those of the plurality of the wordlines 56 a and 56 b in the memory region, they do not operate as thememory cell.

In some embodiments of the present invention, an opening 135 is formedunder the dummy gate line 50 so as to reduce the likelihood that chargesgenerated in etching the isolation layer 106 b will accumulate at afloating gate pattern. Methods of fabricating nonvolatile memory deviceswill be discussed below.

Referring now to FIGS. 3A through 11B, cross-sections illustratingprocessing steps in the fabrication of nonvolatile memory deviceaccording to some embodiments of the present invention will bediscussed. FIGS. 3A through 11A are cross-sections taken along the lineA-A′ of FIG. 2 and FIGS. 3B through 11B are cross-sections taken alongthe line B-B′ of FIG. 2.

As illustrated in FIGS. 3A and 3B, a pad oxide layer 102 is formed onthe substrate 100 and a pad nitride layer 104 is formed on the pad oxidelayer. The pad oxide layer 102 and the pad nitride layer 104 are used asan etch mask for forming a trench in the substrate 100.

Referring now to FIGS. 4A and 4B, a photoresist pattern (not shown) isformed on the pad nitride layer 104. The pad nitride layer 104, the padoxide layer 102 and the substrate 100 are etched in sequence to form thetrench therein. After depositing a high density plasma (HDP) oxide layerfor a trench insulating layer in the trench, a chemical mechanicalpolishing (CMP) process is performed for planarizing a top surfacethereof, to thereby form an isolation layer 106, which defines theactive region of the substrate 100.

Referring now to FIGS. 5A and 5B, the pad oxide layer 102 and the padnitride layer 104, which are used as the etch mask, are selectivelyremoved. A gate insulating layer 108 is formed on the exposed substrate100. In some embodiments of the present invention, the gate insulatinglayer 108 may include a thermal oxide layer. A buffer conductive layer110 is formed on the gate insulating layer 108. The buffer conductivelayer 110 may reduce the likelihood that an oxide layer is additionallyformed on the gate insulating layer 108 in following processes. Thebuffer conductive layer 110 may include, for example, a conductivematerial. In particular, in some embodiments of the present inventionthe buffer conductive layer 110 may include the same material as afloating gate pattern, the formation of which will be discussed below,so that the resistance between the buffer conductive layer 110 and thefloating gate pattern may be as low as possible.

Referring now to FIGS. 6A and 6B, after forming a photoresist pattern(not shown) on the buffer conductive layer 110 and the gate insulatinglayer 108, an opening 135 is formed using, for example, an etchingprocess. The opening 135 may act as a charge pathway, such that chargesgenerated during a subsequent etching process of the isolation layer 106may not accumulate in the floating gate pattern but be discharged intothe substrate 100. This opening 135 is provided over the well contactregion, such that it is formed under the dummy gate line formed in asubsequent process. In some embodiments of the present invention, theopening 135 may be formed such that its width is equal to or smallerthan the width of the dummy gate line.

Referring now to FIGS. 7A and 7B, a floating gate pattern 112 is formedon the resultant structure and is planarized using, for example, achemical mechanical polishing (CMP) process to expose at least a portionof the upper surface of the isolation layer 106. The floating gatepattern 112 may include, for example, a metallic material, dopedpolysilicon, or the like. The floating gate pattern 112 is provided inthe opening 135 and, thus, the floating gate pattern 112 is electricallycoupled to the substrate 100 through the opening 135.

In some embodiments of the present invention, processing steps in thefabrication of memory devices discussed above with respect to FIGS. 3Athrough 7B may be modified by forming the gate insulating layer 108 onthe substrate 100 and patterning the gate insulating layer 108 to formthe opening 135, which exposes at least a portion of the well contactregion of the substrate 100. Thereafter, a conductive layer may beformed on the resultant structure and then the isolation layer may beformed.

Referring now to FIGS. 8A and 8B, a first etching process is performedto remove at least a portion of the isolation layer 106. In someembodiments of the present invention, after the first etching process, asurface of the isolation layer 106 a may be higher than an upper surfaceof the gate insulating layer 108 formed on the substrate 100. The firstetching process may be performed using, for example, a dry etchingprocess or a wet etching process.

Referring to now to FIGS. 9A and 9B, a second etching process isperformed on the remaining portion of the isolation layer 106 a toexpose at least a portion of a side surface of the floating gate pattern112. At this time, a dry etching process having an anisotropic etchingcharacteristic may be used to reduce the likelihood that the gateinsulating layer 108 on the substrate 100 will be etched simultaneouslywith the isolation layer 106 b. In some embodiments of the presentinvention, the charges generated due to the plasma used in the dryetching process may not be accumulated in the floating gate pattern 112,but discharged into the substrate 100 through the opening 135. Althoughthe opening 135 is formed in the well contact region, charges injectedonto the memory region may move into the opening 135 in the well contactregion so that the charges may be discharged into the substrate 100because charges tend to choose the path of least resistance. Therefore,according to some embodiments of the present invention, a breakdownphenomenon may not occur in the gate insulating layer 108 formed on thesubstrate 100.

Referring now to FIGS. 10A and 10B, a dielectric layer 114 and aconductive layer 116 are formed on the resultant structure. Thedielectric layer 114 may include, for example, oxide-nitride-oxide (ONO)layer. A hard mask layer 118 is formed on the conductive layer 116. Thehard mask layer 118 is used as an etch mask for etching the conductivelayer 116 for forming a control gate, the dielectric layer 114 and thefloating gate pattern 112.

Referring now to FIGS. 11A and 11B, a photoresist pattern (not shown) isformed on the hard mask layer 118, and the overlying layers 116, 114,112 and 110 on the gate insulating layer 108 are etched into apredetermined configuration using a hard mask (not shown) formed by thephotoresist pattern, to thereby form the dummy gate line 50, a groundselect line 54 and the plurality of word lines 56 a and 56 b. At thistime, the gate insulating layer 108 acts as an etch barrier layer. Afterforming a mask on the well contact region, an ion implantation processis performed over the memory region to form source/drain regions 140.Although not illustrated in the Figures, after an interlayer insulatinglayer is formed and a contact hole is formed, processing steps forconnecting the source region of the ground select line 54 to a commonsource line 52 are performed. Although it is illustrated as if afloating gate 112 a and the control gate 116 a of the ground select line54 are spaced apart from each other through the dielectric layer 114 a,in some embodiments of the present invention, the floating gate 112 aand the control gate 116 a may be electrically connected to each other.

As illustrated in the figures, the opening 135 extending through thebuffer conductive layer 110 and the gate insulating layer 108 is formedunder the dummy gate line 50 formed on the well contact region, suchthat the dummy gate line 50 is electrically connected to the substrate100 through the opening 135. As discussed above, since the dummy gateline 50 does not operate as a memory cell, there may not be a problem inoperating the memory device even if the substrate 100 is electricallyconnected to the dummy gate line 50. Furthermore, the ground select line54 and the plurality, of the word lines 56A and 56B formed on thesubstrate 100 incorporating the memory region, are electrically isolatedfrom the substrate 100 by the gate insulating layer 108. Therefore, thefloating gate 112 a operates as a memory cell, which functions as a datarecording layer.

Referring now to FIG. 12, a plan view of nonvolatile memory devicesaccording to further embodiments of the present invention will bediscussed. As illustrated in FIG. 12, an opening 145, which is used as acharge pathway during an etching process of an isolation layer, is notformed under a dummy gate line 50′, but it is formed on an active regionbetween the dummy gate lines 50′. The opening 145 is used as the opening145 only during the etching process of the isolation layer and,thereafter, it remains as a concavity 147 (FIG. 16B) on an active regionof a well contact region, whereas the opening 135 discussed above withrespect to FIGS. 3A through 11B remains under the dummy gate line 50after all the processes are completed.

Referring now to the cross-sections of FIGS. 13A to 16B, processingsteps in the fabrication of nonvolatile memory devices according tofurther embodiments of the present invention will be discussed. FIGS.13A through 16A are cross-sections taken along the line A-A′ of FIG. 12and FIGS. 13B through 16B are cross-sections taken along the line B-B′of FIG. 12. The processing steps discussed above with respect to FIGS.3A through 5B are performed and, therefore, the details of theseprocessing steps will not be discussed in detail herein. In particular,an etch mask is formed on a substrate 100′ and the substrate 100′ ispatterned to form a trench therein. Thereafter, an oxide layer is formedin the trench to form an isolation layer 106′. After removing the etchmask, a gate insulating layer 108′ and a buffer conductive layer 110′are formed on the resultant structure, and they are patterned to form anopening 145. At this time, the opening 145 is formed on the activeregion except a portion under the dummy gate line, which will be formedlater. However, this opening 145 may be simultaneously formed under thedummy gate line as well as on the active region.

Referring now to FIGS. 13A and 13B, a floating gate pattern 112′ isformed on the resultant structure. The floating gate pattern 112′includes, for example, a conductive material. Furthermore, the floatinggate pattern 112′ may be electrically connected to the substrate 100′through the opening 145.

Referring now to FIGS. 14A and 14B, charges generated in etching theisolation layer 106′ are not accumulated in the floating gate pattern112′, but discharged into the substrate 100′ through the opening 145.Therefore, it may be possible to reduce the likelihood that thebreakdown phenomenon will be induced in the gate insulating layer 108′.

Referring now to FIGS. 15A and 15B, a dielectric layer 114′ and aconductive layer 116′ are formed on the resultant structure in sequence,and then a hard mask layer 118′ is formed on the conductive layer 116′.The hard mask layer 118′ is used as an etch mask for etching theconductive layer 116′, the dielectric layer 114′ and the floating gatepattern 112′.

Referring now to FIGS. 16A and 16B, a photoresist pattern (not shown) isformed on the hard mask layer 118′ and the overlying layers 116′, 114′,112′ and 110′ on the gate insulating layer 108′ are etched using a hardmask (not shown) formed by the photoresist pattern, to thereby form adummy gate line 50′, a ground select line 54′, and a plurality of wordlines 56 a′ and 56 b′. The gate insulating layer 108′ becomes an etchbarrier layer as stated above. However, since the gate insulating layer108′ is not provided on the opening 145, a portion of the substrate 100′incorporating the well contact region is etched such that a portion ofthe opening 145 remains as a concavity 147. An ion implantation processis performed to form source/drain regions 140′.

According to some embodiments of the present invention, since thecharges generated in etching the isolation layer are not accumulated inthe floating gate pattern, but discharged into the substrate through theopening, it may be possible to reduce the likelihood that breakdown inthe gate insulating layer will occur. Thus, more reliable memory devicesmay be provided according to some embodiments of the present invention.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A method of fabricating nonvolatile memory device, the method comprising: forming an isolation layer on a substrate, the substrate having a memory region and a well contact region and the isolation layer defining an active region of the substrate; forming a gate insulating layer on the active region; and patterning the gate insulating layer to define an opening therein, the opening exposing at least a portion of the well contact region of the substrate; and forming a first conductive layer on the gate insulating layer, the first conductive layer is self-aligned with the active region and is in contact with the well contact region through the opening.
 2. The method of claim 1, further comprising: selectively etching the isolation layer to expose at least a portion of a side surface of the first conductive layer.
 3. The method of claim 2, further comprising: forming a dielectric layer on the first conductive layer; forming a second conductive layer on the dielectric layer; and patterning the dielectric layer and the first and second conductive layers to provide stacked gate electrodes on the memory region and the well contact region of the substrate.
 4. The method of claim 3, wherein the opening is under the stacked gate electrode formed on the well contact region and electrically couples the first conductive layer and the substrate.
 5. The method of claim 3, wherein the opening is outside of the stacked gate electrode formed on the well contact region.
 6. The method of claim 2, wherein forming the gate insulating layer is followed by forming a buffer conductive layer on the gate insulating layer and wherein patterning further comprising patterning the buffer conductive layer to define the opening in the gate insulating layer and the buffer conductive pattern.
 7. The method of claim 6, wherein the selectively etching comprises: etching the isolation layer until a surface of the isolation layer is substantially planar with an upper surface of the first conductive layer; and then etching the isolation layer until at least a portion of the side surface of the first conductive layer is exposed.
 8. The method of claim 7, wherein etching the isolation layer until the side surface of the first conductive layer is exposed comprises an anisotropic dry etching process.
 9. A method of fabricating a nonvolatile memory device, the method comprising: forming a gate insulating layer on a substrate, the substrate having a memory region and a well contact region; patterning the gate insulating layer to define an opening therein, the opening exposing at least a portion of the well contact region of the substrate; forming a first conductive layer on the gate insulating layer; forming an isolation layer on the substrate, the isolation layer defining an active region; and selectively etching the isolation layer to expose at least a portion of a side surface of the first conductive layer.
 10. The method of claim 9, further comprising: forming a dielectric layer on the first conductive layer; forming a second conductive layer on the dielectric layer; and patterning the dielectric layer and the first and second conductive layer to provide stacked gate electrodes on the memory region and the well contact region of the substrate.
 11. The method of claim 10, wherein the opening is under the stacked gate electrode formed on the well contact region and electrically couples the first conductive layer and the substrate.
 12. The method of claim 10, wherein the opening is outside of the stacked gate electrode formed on the well contact region.
 13. The method of claim 9, wherein the opening acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. 